1. Field of the Invention
The present invention relates to operational amplifiers and, more particularly, to CMOS differential amplifiers having DC offset and common-mode voltage control.
2. Background of Related Art
Balanced pairs of transistors, such as CMOS transistors, are often configured as differential pairs and used as common building blocks in amplifier design. In particular, such transistor pairs are typically employed in differential amplifiers to amplify the difference between two input signals. The problems associated with use of CMOS transistors as a differential pair lie in the offset voltage and in the common-mode voltage of each transistor.
A known differential amplifier circuit 10 is schematically depicted in FIG. 1. The circuit 10 is constructed as a first a pair of transistors Q.sub.1 and Q.sub.2 connected to a DC current source I and connected to a second pair of transistors Q.sub.3, Q.sub.4 that may function as a load and/or as a transconductance element, as is known in the art, and which are connected to a voltage source V.sub.dd. Each transistor has a gate, a drain and a source terminal. As shown, Q.sub.1 and Q.sub.2 are operated as a differential pair; a separate input signal is applied to each transistor Q.sub.1 and Q.sub.2 such that a first input signal V.sub.1 is applied to the gate terminal of transistor Q.sub.1 and a second input signal V.sub.2 is applied to the gate terminal of transistor Q.sub.2. The output of the circuit 10 is an amplified signal of the difference between V.sub.1 and V.sub.2. Under ideal conditions, Q.sub.1 and Q.sub.2 are equivalent in size so that their threshold or turn-on voltages are identical. This results in a zero output voltage when the difference between the input signals V.sub.1 and V.sub.2 is zero (e.g., the two signals are identical). In other words, when V.sub.1 -V.sub.2 =0, V.sub.0 should ideally also be zero. However, due to various factors such as manufacturing variables, perfectly matched pairs of transistors are difficult to obtain, thus resulting in a non-zero value of V.sub.0 when the differential input signal is zero. Such a condition detrimentally reduces the dynamic operating range of the circuit 10. In order to obtain as close to a balanced pair of transistors as possible, current techniques physically alter the sizes of the transistors so that the transistors in a balanced pair configuration are matched. This technique typically employs lasers which shave down or trim the dimensions of the transistors and, as can be appreciated, such a procedure is tedious, time consuming and costly.
Another parameter used in designing differential pairs of transistors for use in operational amplifiers is the common mode voltage (CMV) which is the DC value of the output voltage from each transistor in the pair, i.e. the voltage at the drain (D) terminal of Q.sub.1. In practice, it is desirable to design a differential pair with the CMV selected to be a particular value based on predefined criteria or the intended function of the operational amplifier. For example, in some instances it is desired to have a rail-to-rail swing for the signal, e.g. to have the CMV value sit at the halfway point between ground and V.sub.dd.
Known techniques for obtaining a desired CMV value for the differential pair Q.sub.1 and Q.sub.2 involve controlling the voltages applied to the loading transistors Q.sub.3 and Q.sub.4. This is usually accomplished by employing a common mode feedback circuit 20 connected between the source and gate terminals of at least one of the loading transistors (e.g. Q.sub.3). The drawback of such a technique, however, is that it compromises the versatility of the amplifier circuit because the gate terminal of one or more of the loading transistors must be utilized for the feedback circuit. This, of course, prevents the use of such a terminal for the input of an additional signal, e.g. the input of a signal to the gate terminal of Q.sub.3.